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FSW

  • SIDL
    • sim + fsw
    • Shared timer so you can make robust controller and make sure our sim is good
  • HIDL
    • Sim -> FSW -> Hardware -> Sim
    • sim propogates step
    • fsw actuates the step
    • hardware does the step
    • based on hardware update the sim

Ideally want to make the fsw compatible with everything available

Using CPP 23 No STD no memory leaks assigning memory? Free it in the end

IN FSW directory, subdirectory - Comms - handles deserialized incoming udp packets - serialize a new messagefactory template - for each message type: - pt - multivariate bayesian regression - - lc - rtd - tc - for flight also - imu - gyro etc - baro - populate said message fields with correct bitsize ordering - Little-endian ordering system - FSW - WHere all the meat is - Each message will get its own dedicated fileStartup - Each board state heartbeats - Boards wait until server heartbeat — DHCP init

  • Server learns all boards — Uses config file to to map to uses/connected config.yaml

— Server determines contorller actuator board and abort PT board — — If no server, unicast together —— otherwise PT -> server -> controller - Ground - GUI - HIDL/SIDL - Config - utils - postprocess

Commit Rules

CICD - Test Cases, if you fail figure out why you failed - commit early, commit often - dont care about readabilty - valgrind before pushign

Ito's law model everything as an ito's law and find the expected value Allan variance analysis